1. Field of the Invention
The present invention relates to a fabrication method, a fabrication apparatus and a semiconductor package that prevents cracks in the semiconductor package, and in particular, that prevents interface delamination and cracking by performing a coating process.
2. Background of the Related Art
As shown in FIG. 1, one type of related art semiconductor package includes a semiconductor chip 1 fixed to a paddle 2 of a lead frame by an adhesive 3. The pads (not shown) of the semiconductor chip 1 are electrically connected to inner leads 4a of the lead frame by wires 5. Then, the above-described elements are sealingly encapsulated by a molding resin 6, and the outer leads 4b are formed to a desired shape.
In the related art "lead-on-chip" (LOC) package as shown in FIG. 2, inner leads 13a are directly attached to the upper side of the semiconductor chip 11 by a double-sided adhesive insulation tape 12. The inner leads are electrically connected to chip pads (not shown) formed at the center of the semiconductor chip 11 by wires 14. The chip 11, inner leads 13a and wires 14 are encapsulated by molding resin 15. Then, the outer leads 13b are formed into a desired shape according to the requirements of an end user.
However, the above-described semiconductor packages have disadvantages in that an interface isolation and a cracking phenomenon can occur because of a thermal expansion coefficient mismatch between the different materials at the interface between the chip 1 and the paddle 2, at the interface between the paddle 2 and the the molding resin 6, at the interface between the chip 1 and the molding resin 6 and at the interface between the chip 11 and the molding resin 15. In addition, such interface isolation and cracks increase with the duration of the fabrication processes, which increasingly degrades the reliability of the device.
To overcome the above problems, many studies have been conducted. One method of enhancing the strength and adhesive property of the molding resin sealing material was introduced in the industry. In addition, according to U.S. Pat. Ser. No. 5,434,106, a method of coating an aminopropyltriethoxysilane film on an inactive surface of the semiconductor chip (i.e., an area without circuitry) has been introduced.
However, there is a limit in increasing the strength of the molding resin. In addition, as the hardness is increased, the molding resin can be more easily broken. Further, in the case of increasing the adhesive property of the molding resin, proper ejecting and cleaning of the molded package becomes very difficult and many flashes can occur, and the adhesive property of the flashes is increased. Thus, deflashing becomes more difficult.
In addition, the method of coating the lower portion of the semiconductor chip of the LOC type package in U.S. Pat. No. 5,434,106 is limited to only one surface in which the prevention region of the interface isolation/crack is coated on the semiconductor chip. Therefore, the effects are minimized. In addition, after the back grinding process is performed in a wafer state, the coating process has to be performed again, which complicates the fabrication process.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.